Intel Formally Launches GPU D-Series at OCP Global Summit
At the Open Compute Project (OCP) Global Summit 2026, Intel formally introduced its new enterprise AI accelerator family, designated the Intel GPU D-series, led by the GPU D270. Previously tracked under the development codename 'Crescent Island,' the accelerator represents a dedicated pivot toward memory-intensive enterprise inference workloads.
Engineered as a pure compute and inference silicon product, the accelerator strips away traditional 3D graphics and ray-tracing hardware entirely. This architecture dedicates the entire die area to arithmetic throughput, tensor acceleration, and large-context memory handling. Intel confirmed that customer sampling for the GPU D270 is actively underway across hardware partners.
Xe3P Architecture and Scalable Memory up to 480 GB LPDDR5X
The GPU D270 is built on the Xe3P microarchitecture, integrating 32 Xe3P cores, 256 Vector Engines, 256 16-deep systolic XMX engines, and 32 MB of unified L2 cache. The card delivers 1.3 PFLOPS of FP8 compute capability, with native precision support spanning FP64 down to FP4 for heavily quantized deployments.
Rather than relying on cost-prohibitive High Bandwidth Memory (HBM), the architecture utilizes high-density LPDDR5X. Intel's reference design integrates 160 GB of LPDDR5X, while original design manufacturer (ODM) partner configurations scale the onboard memory up to 480 GB per accelerator. The card achieves 1.5 TB/s in aggregate memory bandwidth, packaged within a standard dual-slot, air-cooled PCIe 5.0 x16 envelope rated at 350 watts TDP.
Targeting Billion-Parameter Serving and Agentic Memory
Intel positioned the accelerator specifically for memory-capacity bottlenecks, particularly multi-tenant agent systems and expansive token context windows that require substantial Key-Value (KV) cache headroom. According to company presentations, a single GPU D270 card can host and serve models up to 300 billion parameters directly in local device memory.
When scaled across an eight-accelerator node, the cluster can host models exceeding 1 trillion parameters without partitioning across multiple chassis. However, critical commercial details remain unconfirmed: Intel has not published retail pricing or a definitive general availability date, and independent third-party performance benchmarks have yet to be published to verify actual serving latency under production loads.
Practitioner Reactions: Capacity Density Versus Bandwidth Compromises
Hardware practitioners and systems engineers quickly honed in on the architectural trade-offs inherent in pairing LPDDR5X with an inference-focused core. While the 1.5 TB/s throughput is significantly lower than high-end HBM3e or HBM4 alternatives—such as Intel's own Gaudi 3, which delivers 3.7 TB/s—engineers recognized the immense value of having 480 GB of addressable memory inside a modest 350W thermal envelope for large-batch or multi-tenant agent serving.
Practitioners compared the setup to high-end unified memory architectures, including workstation-class systems like Apple silicon workstations or recent high-memory Ryzen configurations. The consensus highlights that for organizations requiring dense KV cache retention rather than raw peak FLOPS throughput, Intel's choice provides a pragmatic, air-cooled path to run 70B to 300B parameter checkpoints without structural facility overhauls.
Strategic Significance for Thai Enterprise Infrastructure
For enterprise CIOs and datacenter operators in Thailand, the GPU D270 introduces an appealing total cost of ownership (TCO) equation. Most commercial colocation and private on-premises facilities in the country are built around standard hot/cold-aisle air cooling. Procuring top-tier HBM accelerators that demand facility-level liquid cooling loops involves steep capital expenditure beyond hardware purchase costs.
A PCIe-standard, 350W board that drops directly into conventional rackmount chassis enables Thai financial institutions, telecommunications providers, and public sector agencies to deploy sovereign, on-premises 70B+ LLM pipelines aligned with personal data protection regulations (PDPA). Decision-makers should nevertheless monitor formal pricing and latency benchmarks to determine whether the 1.5 TB/s bandwidth meets their interactive user-facing latency thresholds before committing capital.
Packing up to 480 GB of memory onto an air-cooled card lowers infrastructure friction for enterprise operators aiming to serve long-context 70B to 300B parameter models without costly liquid cooling retrofits.